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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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Designer'sTM Data Sheet
TMOS VTM SOT-223 for Surface Mount
N-Channel Enhancement-Mode Silicon Gate
TMOS V is a new technology designed to achieve an on-resistance area product about one-half that of standard MOSFETs. This new technology more than doubles the present cell density of our 50 and 60 volt TMOS devices. Just as with our TMOS E-FET designs, TMOS V is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. New Features of TMOS V * On-resistance Area Product about One-half that of Standard MOSFETs with New Low Voltage, Low RDS(on) Technology * Faster Switching than E-FET Predecessors Features Common to TMOS V and TMOS E-FETS * Avalanche Energy Specified * IDSS and VDS(on) Specified at Elevated Temperature * Static Parameters are the Same for both TMOS V and TMOS E-FET * Available in 12 mm Tape & Reel Use MMFT3055VLT1 to order the 7 inch/1000 unit reel Use MMFT3055VLT3 to order the 13 inch/4000 unit reel MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating Drain-to-Source Voltage Drain-to-Gate Voltage (RGS = 1.0 M) Gate-to-Source Voltage - Continuous Gate-to-Source Voltage - Non-repetitive (tp 10 ms) Drain Current - Continuous Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 s) Total PD @ TA = 25C mounted on 1" sq. Drain pad on FR-4 bd material Total PD @ TA = 25C mounted on 0.70" sq. Drain pad on FR-4 bd material Total PD @ TA = 25C mounted on min. Drain pad on FR-4 bd material Derate above 25C Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 25 Vdc, VGS = 5.0 Vdc, Peak IL = 3.4 Apk, L = 10 mH, RG = 25 ) Thermal Resistance - Junction to Ambient on 1" sq. Drain pad on FR-4 bd material - Junction to Ambient on 0.70" sq. Drain pad on FR-4 bd material - Junction to Ambient on min. Drain pad on FR-4 bd material Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds
TM
MMFT3055VL
TMOS POWER FET 1.5 AMPERES 60 VOLTS RDS(on) = 0.140 OHM
D 4 G S 1 2 3 CASE 318E-04, Style 3 TO-261AA
Symbol VDSS VDGR VGS VGSM ID ID IDM PD
Value 60 60 15 20 1.5 1.2 5.0 2.1 1.7 0.94 6.3 - 55 to 175 58
Unit Vdc Vdc Vdc Vpk Adc Apk Watts
mW/C C mJ C/W
TJ, Tstg EAS
RJA RJA RJA TL
70 88 159 260 C
Designer's Data for "Worst Case" Conditions -- The Designer's Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit curves -- representing boundaries on device characteristics -- are given to facilitate "worst case" design. E-FET, Designer's, and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
REV 1
(c) Motorola TMOS Motorola, Inc. 1996
Power MOSFET Transistor Device Data
1
MMFT3055VL
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) Gate-Body Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (1) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static Drain-to-Source On-Resistance (VGS = 5.0 Vdc, ID = 0.75 Adc) Drain-to-Source On-Voltage (VGS = 5.0 Vdc, ID = 1.5 Adc) (VGS = 5.0 Vdc, ID = 0.75 Adc, TJ = 150C) Forward Transconductance (VDS = 8.0 Vdc, ID = 1.5 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (2) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Gate Charge (VDS = 48 Vdc, ID = 1.5 Adc, VGS = 5.0 Vdc) (VDD = 30 Vdc, ID = 1.5 Adc, VGS = 5.0 Vdc, RG = 9.1 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (1) (IS = 1.5 Adc, VGS = 0 Vdc) (IS = 1.5 Adc, VGS = 0 Vdc, TJ = 150C) VSD -- -- trr (IS = 1.5 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) (1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%. (2) Switching characteristics are independent of operating junction temperature. (3) Reflects typical values. Max limit - Typ Cpk = 3 x SIGMA LD -- LS -- 7.5 -- 4.5 -- nH nH ta tb QRR -- -- -- -- 0.82 0.68 41 29 12 0.066 1.2 -- -- -- -- -- C ns Vdc -- -- -- -- -- -- -- -- 9.5 18 35 22 9.0 1.0 4.0 3.5 20 40 70 40 10 -- -- -- nC ns (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Ciss Coss Crss -- -- -- 350 110 29 490 150 60 pF (Cpk 2.0) (3) VGS(th) 1.0 -- (Cpk 2.0) (3) RDS(on) VDS(on) -- -- gFS 1.0 -- -- 3.5 0.25 0.24 -- mhos -- 1.5 3.7 0.125 2.0 -- 0.14 Vdc mV/C Ohm Vdc (Cpk 2.0) (3) V(BR)DSS 60 -- IDSS -- -- IGSS -- -- -- -- 10 100 100 nAdc -- 65 -- -- Vdc mV/C Adc Symbol Min Typ Max Unit
Reverse Recovery Time
2
Motorola TMOS Power MOSFET Transistor Device Data
MMFT3055VL
TYPICAL ELECTRICAL CHARACTERISTICS
4 I D , DRAIN CURRENT (AMPS) 3.5 3 2.5 2 1.5 2.5 V 1 0.5 2V 0 0 1 2 3 4 5 6 7 8 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 9 10 6V 4.5 V 3.5 V TJ = 25C 3V I D , DRAIN CURRENT (AMPS) 4 3.5 3 2.5 2 1.5 1 0.5 0 0 25C TJ = - 55C 0.5 1 1.5 2 100C 2.5 3 3.5 4 4.5 5 5.5 6 6.5 VDS 10 V
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
Figure 1. On-Region Characteristics
R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)
Figure 2. Transfer Characteristics
0.25 0.225 0.2 0.175 0.15 0.125 0.1 0.075 0.05 0.025 0 0 0.5 1 2 2.5 1.5 3 ID, DRAIN CURRENT (AMPS) 3.5 4 - 55C 25C TJ = 100C VGS = 5 V
0.25 0.225 0.2 0.175 0.15 0.125 0.1 0.075 0.05 0.025 0 0 0.5 1 1.5 3 2 2.5 ID, DRAIN CURRENT (AMPS) 3.5 4 15 V VGS = 10 V TJ = 25C
Figure 3. On-Resistance versus Drain Current and Temperature
Figure 4. On-Resistance versus Drain Current and Gate Voltage
RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)
2.0 1.8 1.6 I DSS , LEAKAGE (nA) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 - 50 - 25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (C) 150 175 VGS = 5 V ID = 0.75 A
1000 VGS = 0 V
TJ = 125C 100
100C 10
1
0
10 30 40 20 50 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
60
Figure 5. On-Resistance Variation with Temperature
Figure 6. Drain-To-Source Leakage Current versus Voltage
Motorola TMOS Power MOSFET Transistor Device Data
3
MMFT3055VL
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP)
1000 900 800 C, CAPACITANCE (pF) 700 600 Crss 500 400 300 200 100 0 10 5 VGS 0 VDS 5 10 15 20 Coss Crss 25 Ciss Ciss
The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.
VDS = 0 V
VGS = 0 V
TJ = 25C
GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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Motorola TMOS Power MOSFET Transistor Device Data
MMFT3055VL
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 10 9 8 7 6 5 4 3 2 1 0 0 1 Q3 2 3 4 5 6 VDS 7 Q1 Q2 VGS QT 30 27 24 21 18 15 12 9 ID = 1.5 A 6 TJ = 25C 3 0 8 9 10 1000 VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) VDD = 30 V ID = 1.5 A VGS = 5 V TJ = 25C
t, TIME (ns)
100 td(off) tf tr td(on)
10
1
1
10 RG, GATE RESISTANCE (OHMS)
100
QT, TOTAL CHARGE (nC)
Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge
Figure 9. Resistive Switching Time Variation versus Gate Resistance
DRAIN-TO-SOURCE DIODE CHARACTERISTICS
1.6 1.4 I S , SOURCE CURRENT (AMPS) 1.2 1 0.8 0.6 0.4 0.2 0 0.6 0.625 0.65 0.675 0.7 0.725 0.75 0.775 0.8 0.825 0.85 VGS = 0 V TJ = 25C
VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain- to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.
Motorola TMOS Power MOSFET Transistor Device Data
5
MMFT3055VL
SAFE OPERATING AREA
10 I D , DRAIN CURRENT (AMPS) VGS = 15 V SINGLE PULSE TC = 25C 60 E , SINGLE PULSE DRAIN-TO-SOURCE AS AVALANCHE ENERGY (mJ) ID = 1.5 A 50 40 30 20 10 0 10 ms
1 100 ms 500 ms 0.1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1 1s dc 10 100
0.01
25
50
75
100
125
150
175
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
TJ, STARTING JUNCTION TEMPERATURE (C)
Figure 11. Maximum Rated Forward Biased Safe Operating Area
Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature
1 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE
D = 0.5 0.2 0.1 0.05 0.02 0.01
0.1
0.01
0.001 SINGLE PULSE
0.0001 1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01 t, TIME (s)
1.0E+00
1.0E+01
1.0E+02
1.0E+03
Figure 13. Thermal Response
di/dt IS trr ta tb TIME tp IS 0.25 IS
Figure 14. Diode Reverse Recovery Waveform
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Motorola TMOS Power MOSFET Transistor Device Data
MMFT3055VL
INFORMATION FOR USING THE SOT-223 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection interface
0.15 3.8 0.079 2.0
between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.
0.091 2.3 0.079 2.0 0.059 1.5 0.059 1.5
0.091 2.3
0.248 6.3
0.059 1.5
inches mm
SOT-223
SOT-223 POWER DISSIPATION
The power dissipation of the SOT-223 is a function of the drain pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the SOT-223 package, PD can be calculated as follows: PD = TJ(max) - TA RJA dissipation can be increased. Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. A graph of RJA versus drain pad area is shown in Figure 17.
160 R JA , Thermal Resistance, Junction to Ambient ( C/W) Board Material = 0.0625 G-10/FR-4, 2 oz Copper 0.8 Watts 120 1.25 Watts* 100 *Mounted on the DPAK footprint 80 0.0 0.2 0.4 0.6 A, Area (square inches) 0.8 1.0 1.5 Watts TA = 25C
140
The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 943 milliwatts. PD = 175C - 25C = 943 milliwatts 159C/W
The 159C/W for the SOT-223 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 943 milliwatts. There are other alternatives to achieving higher power dissipation from the SOT-223 package. One is to increase the area of the drain pad. By increasing the area of the drain pad, the power
Figure 15. Thermal Resistance versus Drain Pad Area for the SOT-223 Package (Typical) Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal CladTM. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint.
Motorola TMOS Power MOSFET Transistor Device Data
7
MMFT3055VL
SOLDER STENCIL GUIDELINES
Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. A solder stencil is required to screen the optimum amount of solder paste onto the footprint. The stencil is made of brass or stainless steel with a typical thickness of 0.008 inches. The stencil opening size for the SOT-223 package should be the same as the pad size on the printed circuit board, i.e., a 1:1 registration.
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C.
* The soldering temperature and time shall not exceed * When shifting from preheating to soldering, the maximum * After soldering has been completed, the device should be
allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. temperature gradient shall be 5C or less. 260C for more than 10 seconds.
8
Motorola TMOS Power MOSFET Transistor Device Data
MMFT3055VL
TYPICAL SOLDER HEATING PROFILE
For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 18 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The
STEP 1 PREHEAT ZONE 1 "RAMP" 200C STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP"
line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177 -189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.
STEP 5 STEP 4 HEATING HEATING ZONES 3 & 6 ZONES 4 & 7 "SPIKE" "SOAK" 170C 160C STEP 6 STEP 7 VENT COOLING 205 TO 219C PEAK AT SOLDER JOINT
DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C
150C 140C
100C 100C
SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)
DESIRED CURVE FOR LOW MASS ASSEMBLIES 50C
TIME (3 TO 7 MINUTES TOTAL)
TMAX
Figure 16. Typical Solder Heating Profile
Motorola TMOS Power MOSFET Transistor Device Data
9
MMFT3055VL
PACKAGE DIMENSIONS
A F
4
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH.
S
1 2 3
B
D L G J C 0.08 (0003) H M K
INCHES DIM MIN MAX A 0.249 0.263 B 0.130 0.145 C 0.060 0.068 D 0.024 0.035 F 0.115 0.126 G 0.087 0.094 H 0.0008 0.0040 J 0.009 0.014 K 0.060 0.078 L 0.033 0.041 M 0_ 10 _ S 0.264 0.287 STYLE 3: PIN 1. 2. 3. 4.
MILLIMETERS MIN MAX 6.30 6.70 3.30 3.70 1.50 1.75 0.60 0.89 2.90 3.20 2.20 2.40 0.020 0.100 0.24 0.35 1.50 2.00 0.85 1.05 0_ 10 _ 6.70 7.30
GATE DRAIN SOURCE DRAIN
CASE 318E-04 ISSUE H
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 or 602-303-5454 MFAX: RMFAX0@email.sps.mot.com - TOUCHTONE 602-244-6609 INTERNET: http://Design-NET.com
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MMFT3055VL/D Motorola TMOS Power MOSFET Transistor Device Data
*MMFT3055VL/D*

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